A 12T Low-Power Standard-Cell Based SRAM Circuit for Ultra-Low-Voltage Operations

Ultra-low voltage ultra-low power on-chip memory circuits are highly desirable for portable and wearable applications. A new twelve-transistor (12T) Standard-Cell based Memory (SCM) circuit is proposed in this paper. Two gating transistors are used for each column of SRAM cells to achieve high area efficiency and low write energy consumption. Two-stage read-out scheme is used to reduce both the read delay and energy consumption. The read and write energy consumption per operation is reduced by up to 91.8% and 45.6%, respectively, as compared to the previously published SCM circuit in a 65-nm CMOS technology. The read delay and cell layout area are also reduced by up to 92.7% and 22.9%, respectively, by the proposed SCM circuit compared to the previously published SCM circuit. Furthermore, the standard cell based topology guarantees high data stability and write ability with the proposed 12T SRAM cell.