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SP 24.6: A 500MHz 4Mb CMOS Pipeline-Burst Cache SRAM with Point-to-Point Noise Reduction Coding 110
SP 24.6: A 500MHz 4Mb CMOS Pipeline-Burst Cache SRAM with Point-to-Point Noise Reduction Coding 110
1997
Kazuyuki Nakamura
Koichi Takeda
Hideo Toyoshima
Kenji Nodal
Hiroaki Ohkubo
Tetsuya Uchida
Toshiyuki Shimizu
Toshiro Itani
K. Tokashiki
Koji Kishimoto
Keywords:
Noise reduction
Parallel computing
Point-to-point
Computer science
Pipeline burst cache
CMOS
Electronic engineering
Static random-access memory
Computer hardware
Coding (social sciences)
Correction
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