Parallel Processor Array For High Speed Path Planning

The first integration of a 24 x 25 array of processors for high speed optimal path planning is reported. Based on programmed terrain costs (traversal time), the IC determines, in parallel, the fastest routes from a selected starting point(s) to all other points on a given tcrrain. The chip has hQen successfully tested at a 7 MHz clock frequency, with typical path determination requiring 230 lis, resulting in a four order of magnitude speed-up over currmt sofhvare-hasQd shortmtroute techniques.