An mm-Wave Synthesizer with Low In-Band Noise and Robust Locking Reference-Sampling PLL

A two stage mm-wave frequency synthesizer with low in-band noise and robust frequency locking is presented in this paper. A type-I reference sampling PLL is utilized in the first stage to provide low in-band noise while achieving robust locking. A reshaping buffer is implemented to reduce the rising time on the reference clock, which relaxes the requirement on sampling capacitor and allows smaller capacitor size for equivalent in-band noise level. It generates a 9GHz intermediate clock as the reference for the second stage injection locked (IL) VCO for a 4 times frequency multiplication to generate 36GHz frequency. The wideband injection is assisted by a low power auxiliary frequency tracking loop. The chip was fabricated in a 45nm SOI CMOS technology and achieves 227fs jitter, -240dB FoM at 35.84GHz with total power consumption of 20.6mW.