Memory cell arrangement, method of controlling a memory cell, memory array, A method of operating a memory array and electronic device

Memory cell array (200 '; 300') comprising: • a substrate (201; 301); • a memory cell (200; 300) having a charge storing memory cell structure (210; 310), a select structure (220; 320), a first source / drain region (202; 302) extending (near the select 220; 320 ), and a second source / drain region (203; 303) extending away (of the select 220; 320) is located, comprising wherein the select structure (220; 320), a select gate (221; 321) which is configured as a spacer and laterally spaced from a side wall of the charge-storing memory cell structure (210; 310); • a first doping well (231; 331) and a second doping well (232; 332), wherein the charge storing memory cell structure (210; 310) in and / or over the first dopant well (231; 331) is arranged, wherein the first doping well ( is positioned 301); 231; 331) in the second doping well (232; 332) is arranged, and wherein the second dopant well (232; 332) in the substrate (201; and is programmed or erased (250; 350) • a control circuit which is connected to the memory cell (200; 300) is coupled and is adapted to the memory cell (200;; 300) for controlling such that the charge storing memory cell structure (310 210) by means of charging or discharging of the charge-storing memory cell structure (210; 310) via at least the first dopant well (231; 331); • wherein the control circuit (250; 350) is adapted to the memory cell (200; 300) to control so that the charge storing memory cell structure (210; 310) is programmed by a source side injection mechanism.