Numerical Simulation and Optimization of An a-ITZO TFT Based on a Bi-Layer Gate Dielectrics

This work is an optimization study by numerical simulation of the performance of a bottom gate amorphous indium tin zinc oxide thin film transistor (a-ITZO TFT) using SILVACO-ATLAS software. The optimization process is focused on the gate dielectric conception, namely, thicknesses, number of layers and materials. The electrical characteristics calculated are the gate capacitance per unit area (\( C_{i} \)), the on-current (\( I_{\rm{on}} \)), the on–off current (\( I_{\rm{on}} /I_{\rm{off}} \)) ratio, the threshold voltage (\( V_{\rm{T}} \)), the field-effect mobility (\( \mu_{\rm{FE}} \)), the sub-threshold swing (\( {\hbox{SS}} \)) and the resistivity (\( \rho \)) of the a-ITZO channel. The obtained results indicate that using a bi-layer dielectrics (SiO2/HfO2) with a relatively high thickness (\( {\hbox{BDT}} = 70\;{\hbox{nm}} \)) improves the electrical response compared to TFT based on the mono-layer dielectric, for the same physical thickness, and the optimized outputs obtained are \( C_{i} = 3.45 \times 10^{ - 7} \;{\hbox{F/cm}}^{2} \), \( I_{\rm{on}} = 4.12 \times 10^{ - 5} \;{\hbox{A}} \), \( I_{\rm{on}} /I_{\rm{off}} = 4.67 \times 10^{8} \), \( V_{\rm{T}} = - {\kern 1pt} 0.45\;{\hbox{V}} \), \( \mu_{\rm{FE}} = 29.34\;{\hbox{cm}}^{2} \; {\hbox{V}}^{ - 1} \;{\hbox{s}}^{ - 1} \), \( {\hbox{SS}} = 6.42 \times 10^{ - 2} \;{\hbox{V/dec}} \), and \( \rho = 2.60 \times 10^{ - 2} \;\varOmega \;{\hbox{cm}} \).