a-Si:H TFT-based gate driver circuit using Q node as both pull-up and hold-down controller

We propose a new gate driver circuit, in which the Q node can be operated as a pull-up either as a hold-down controller. The number of transistors for the QB nodes is reduced because the one QB node can be replaced by the pull-up unit of the Q node. With an additional VOUT pull-down unit designed using only two transistors and one capacitance, we can control the discharge interval of the VOUT node to 100% duty ratio. Despite the simplified circuit configuration, the VOUT characteristic is almost the same as that of a conventional circuit with an AC-driven structure using one Q node, and two or more QB nodes. Our simulation results show that the VH voltage operates at +28 V from the 1071st to 1080th VOUT and the rising/falling time is less than 1 μs. To verify the reliability of this circuit, we further confirmed the VOUT according to the change in the threshold voltage (VTH). The proposed circuit can be operated even when the VTH is shifted to +20.5 V from the initial value (VTH = +1.09 V). Further, the VOUT characteristic is not degraded although the VTH was shifted by +18.5 V for the pull-up unit (TFT's ΔVTH except for pull-up unit: +2 V), and the rising/falling time were confirmed to be less than 3.2 μs.