Asynchronous time-based imager with DVS sharing

In the asynchronous time-based image sensor (ATIS) pixel, capture is performed only when a significant luminance change is detected, thus avoiding redundant transmission of data. Furthermore, luminance capture is performed by generating events when the photodiode voltage crosses two thresholds, at the pixel level, which contributes to a high dynamic range in image capture. The ATIS disadvantages are large pixel area and low fill factor. In order to reduce the pixel area, we propose the design of an ATIS in which the dynamic vision sensor (DVS) module is shared by a block of capture modules. A pixel with a 2 $$\times$$ 2 sharing block has roughly 29% fewer components than a pixel with one DVS module per capture module. A Verilog-A model of the proposed circuit is presented and compared to the electrical (device-level) model. Due to the mixed-signal nature of the circuit, the Verilog-A is an important tool for increasing simulation speed. We show that the Verilog-A model simulation of a 4 $$\times$$ 4 matrix is 70% faster than the electrical device-level simulation, while yielding similar reconstruction results.