Combating NBTI-induced aging in data caches

The negative bias temperature instability (NBTI) in CMOS devices is one of most prominent sources of aging mechanisms, which can induce severe threats to the reliability of modern processors at deep submicron semiconductor technologies. Due to the unbalanced duty cycle ratio of the SRAM cells, the data cache suffers a heavy NBTI stress and this will further exacerbate the aging effect in the data cache. In this paper, an aging-aware design is proposed to combat the NBTI-induced aging in the data cache. First, the detailed lifetime behaviors of the cachelines in the data cache are studied. Then, different schemes are proposed to mitigate the negative aging effects by balancing the duty cycle ratio of the SRAM cells in the cachelines according to their different lifetime phases. By applying our proposed idle-time-based cacheline invalidation, early write-back, and bit-flipping schemes, the duty cycle ratio of the data cache can be well balanced. By adopting the drowsy scheme for invalidated cachelines, our design can also reduce the power consumption significantly, which will further optimize the thermal behavior and aging effect of data caches.