The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET

In planar MOSFET, the optimization of finger length should be carried out with considering f T , f max and flicker noise because the noise degradation at STI edge effect appears below 1µm. In FinFET, the optimization of not only finger length but also the distance between gate and source, drain contact region and fin pitch are necessary to reduce parasitic resistance and capacitance. According to our measurement results, the flicker noise of FinFET decreases with scaling of fin width and it is possible to satisfy the 24nm technology node requirement in ITRS roadmap 2011 at fin width below 20nm.