High Density Silicon Substrates for Processor-Memory Integration

In this paper, we demonstrate a polymer-based silicon substrate for high performance computer system with 3 redistribute layers and 1 under-bump-metallization (UBM) layer on one side. The design, process and test of this kind of high density silicon substrate used to integrate CPU and DDR3 are present. The minimum line/space is 10/10μm, and the typical thickness of copper traces and polymer dielectrics between copper layers is 5μm and 8μm respectively. The electrical and mechanical characteristics of the silicon substrate were studied. The insert loss of transmission lines less than 0.4dB at 2.5GHz. To evaluate the qualification of UBM layer, the wire-bonding pull strength of 25μm gold wire and the wettability and solder-bonding strength of silicon substrates were demonstrated. After 100 thermal cycles from −65°C to 150°C, No obvious changes can be seen in all 10 samples.