Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures

This paper explores approximate adders (AA) in a harmonic elimination system using Least Mean Square (LMS) filters. We study the impact of the AA Lower-Part-Or Adder (LOA), Error Tolerant Adder (ETA-I), Truncation adder (Trunc), and Copy adder in the system's accuracy, power dissipation, and circuit area. The adders' approximate part varies the approximation level parameter (K) from 1 to 8. The Root-Mean-Square Error and Mean Absolute Error metrics show that the filtering is efficient for all circuits with $K$ =4. The results highlight the Copy adder (K=4), using the operand B, as the most efficient adder to be applied in the harmonic elimination system presenting 7.5% less circuit area and 21.8% less power dissipation than the one with precise adders.