Contact resistance of solder bump with low cost photosensitive polyimide for high performance SoC

One of technical hurdles in far back-end of line (FBEOL) process is to assure lower solder bump contact resistance (Rc) associated with photosensitive polyimide (PSPI) and under bump metal (UBM) process. Often, higher bump Rc results in low Vcc shift fails in high performance SoC product. With palpable understanding of outgassing behaviors of PSPI and meticulous characterization of degassing phenomena linked to plasma etch with physical vapor deposition (PVD), we successfully achieved < 10mΩ bump Rc even with a low cost PSPI without an existing PVD refurbishment. From photo process to package reliability, a far back-end process optimization for cost effective bump production will be presented.