An FPGA Accelerator for Bayesian Network Structure Learning with Iterative Use of Processing Elements

A Bayesian network is one of the graphical models that represent the causality or correlation relationship among multiple observed phenomena. The structure learning of this network is generally NP difficult, and the computational time to obtain an approximate solution becomes huge. This paper proposes an FPGA accelerator for structure learning of Bayesian networks. The proposed method employs a dataflow type architecture and executes processes without dependency in dynamic programming in parallel. By iteratively using processing elements at each processing stage, we can efficiently use limited resources while taking advantage of the parallel performance of FPGAs. We implemented the proposed method for Xilinx Alveo U200 using high-level synthesis. Evaluation results showed that we achieved up to 12.6 times faster than single-core execution of software and up to 2.98 times faster than on multi-core execution. We further applied the proposed method to the Local-to-Global algorithm and achieves 8.6 times faster than the software execution in the structure learning of a practical network with 37 nodes.