FPGA-Based High-Resolution DPWM Scheme Using Interleaving of Phase-Shifted Clock Pulses

The digital pulse width modulation (DPWM) technique is used to generate high-frequency pulses to feed gate driver circuit of semiconductor switches in switch mode power converters. On-time of pulses can be modulated with the help of a digital control signal. The proportional change in pulse width, with the change in lowest significant bit (LSB) of control signal, gives resolution of DPWM which is generally restricted by clock frequency and number of bits used. This paper proposes a new technique to enhance the resolution of DPWM by taking the advantage of FPGA’s advanced clock management capabilities. A 13-bit DPWM scheme with 45° interleaving of phase-shifted clock pulses is implemented on a Spartan-3AN FPGA kit using 10 MHz clock frequency to obtain the DPWM resolution of 12.5 ns, which is 8 times better than that obtained using a simple counter-based architecture.