Low-cost dual-stage offset-cancelled sense amplifier with hybrid read reference generator for improved read performance of RRAM at advanced technology nodes

In this work, two process-variation-tolerant schemes for a current-mode sense amplifier (CSA) of RRAM were proposed: (1) hybrid read reference generator (HRRG) that tracks Process-Voltage-Temperature (PVT) variations and solves the nonlinear issue of the RRAM cells; (2) a two-stage offset-cancelled current sense amplifier (TSOCC-SA) with only two capacitors achieves a double sensing margin and a high tolerance of device mismatch. The simulation results in 28 nm CMOS technology show that the HRRG can provide a read reference that tracks PVT variations and solves the nonlinear issue of the RRAM cells. The proposed TSOCC-SA can tolerate over 64% device mismatch.