Low Power Circuit Topologies for Digital-to-analog Converters with a Mm-wave Sampling Clock

This thesis describes the design of an 8-bit, 75GS/s, full-rate, low-power DAC in 55nm SiGe BiCMOS process. This is the highest sampling frequency (75GHz) broadband DAC to the best of the author's knowledge. It has an output swing of 1.2Vppd, which is sufficient to directly drive high performance VCSELs for short-reach data center communication links. The low power circuit topologies minimize the power consumption of the DAC to%%%%M.A.S.