An FPGA-Oriented FFT Algorithm for Sigma-Delta Signals

Among other uses, oversampling can be useful for systems that aim to accurately estimate the time delay between two signals. Due to the simplicity of its implementation, \(\varSigma \varDelta \) analog-to-digital converters have been largely used when oversampled signals are required. In this work, two methods for parallel evaluation of the discrete Fourier transform (DFT) of \(\varSigma \varDelta \) signals are presented, targeting frequency domain analysis of oversampled signals. The basic proposed method relies on the partial storage of DFT outputs in memories, considering binary inputs and using a technique named bitstream decomposition to reduce the dimensionality. Additionally, the basic method has been combined to the Cooley–Tukey algorithm to derive a more efficient method. When compared to conventional strategies to compute partial DFTs sequentially, the proposed methods had shown similar results, using feasible memory resources. However, the method allows highly parallel implementations with linear increase in performance as new processing units are added. It has been shown that its implementation on FPGA not only may improve performance but may also reduce memory utilization in more than 80%, enabling low resource FPGAs to compute the FFT of oversampled \(\varSigma \varDelta \) sequences.