Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

Jose Á. Díaz-Madrid,G. Domenech Asensi,J. Javier Martínez-Álvarez,Juan Zapata Pérez,Ramón Ruiz Merino

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

2020

Jose Á. Díaz-Madrid
G. Domenech Asensi
J. Javier Martínez-Álvarez
Juan Zapata Pérez
Ramón Ruiz Merino

This work has been partially funded by Spanish Ministerio de Ciencia e Innovaci´on (MCI), Agencia Estatal de Investigaci´on (AEI) and European Region Development Fund (ERDF/FEDER) under grant RTI2018-097088-BC33

Keywords:

Biasing
Electronic engineering
Joint Implementation
Mathematics
Control theory

Correction
Source
Cite
Save
Machine Reading By IdeaReader

References

Citations