A 68–79 GHZ 15.6DBM Power Amplifier in 65NM CMOS

This paper presents a 68–79 GHz fully integrated power amplifier (PA) in 65nm CMOS technology. The PA is designed with three-stage pseudo-differential common source amplifiers with neutralization capacitors, and transformer-based matching networks for improving matching and linearity. With series power combining, the combiner and balun are merged into one transformer, and this topology improves efficiency of power combining, and achieves compact area. Measurement results show that the PA delivers a saturated output power of 15.6dBm with 17% peak PAE. the output 1-dB compression point $(\mathbf{P}_{\text{ldB}})$ is 12.6dBm. The maximum power gain is 22dB, and 3dB bandwidth of 68–79 GHz. The core area of the PA is only O.14mm 2 without PADs. The power consumption is 195mW under the supply voltage of 1V.