Retention Enhancement through Architecture Optimization in Junctionless Capacitorless DRAM

The work shows the significance of device architecture to enhance the Retention Time (RT) of Junctionless Capacitorless Dynamic Random Access Memory (1T-DRAM). The conduction and storage regions of the DRAM are segregated through an oxide. The top (n-type) region is utilized for conduction while back region (p-type) for charge storage. A potential well, required to store charges, is also achieved through a Metal-Oxide-Semiconductor (MOS) effect. A maximum RT of $\sim 3.8\mathrm{s}$ is achieved with gate length of 200 nm and is scaled down to 10 nm with RT of $\sim 1$ ms at $85^{\circ}\mathrm{C}$. The significance of scaling down total length and thickness is examined. It is possible to scale the bias required to perform Write “1” operation (generation of holes) through Band-to-Band-Tunneling (BTBT) to 0.5 V for gate length of 25 nm with RT of $\sim 220$ ms at $85^{\circ}\mathrm{C}$.