Integer linear programming based fault-tolerant topology synthesis for application-specific NoC

In nano era, fault tolerance has become a significant challenge for IC designers. Even a single link failure on NoC can halt communication between application modules, which makes the entire chip lose efficacy. In this paper, considering link failures, we propose an integer linear programming (ILP) based method to generate K fault-tolerance topologies for application specific NoCs (ASNoC). Compared with the FTTG method, which can generate only one-link failure tolerance topologies, the proposed mehtod show better energy efficiency and average hops, and can scale upward to generate K (K > 1) link fault-tolerance topologies.