New Register Configuration Solution for High Speed IO Test

With the development of chip test technology, high speed IO test gradually convert from at speed test to abist test. ATE needs to configure thousands of registers by d2s during abist test, which brings low debug efficiency and the risk that the amount of generated pattern exceed the 93K upper limit. This paper proposes a new register configuration solution which generate the pattern in offline mode instead of traditional way. Meanwhile, this paper designs a software tool to generate the pattern in offline mode. In this tool, the registers data and address information will be parsed, and the JTAG protocol frame format constructed based on the information provided by the user. The pattern generator will create the main pattern, burst pattern and pattern master file based on the constructed data structure and protocol frame format. A new pattern generation mode was developed namely multi-write or multi-read. A big main pattern will be created instead of a series of small pattern of one suite in the new mode. The actual result shows that the debug efficiency improves 86.6%, the pattern number reduce 40%, and the pattern execution efficiency improve 69%.