Sleep-Transistor Based Power-Gating Tradeoff Analyses

Power-gating is a promising leakage-reduction technique in recent sub-100nm semiconductor technologies but its efficiency and usability depends on several parameters. Beside the technology node size and related parameters (e.g. process corner) it also depends on the switch implementation scheme (e.g. header vs. footer device, single vs. double cutoff), the sleep transistor sizing, and on dynamic parameters such as the supply voltage. In this work, typical sleep-transistor based power-gating schemes are applied to RT-level components and leakage reductions, break-even-, and wake-up-times are traded off for relevant parameters and possibilities as well as limitations of these schemes are evaluated. It is shown that the break-even time varies up to a factor of 4 and the wake-up time up to a factor of 6 solely due to the power gating scheme selection while the leakage reduction is above 95% in all cases.