TSV process-induced MOS reliability degradation

Process-induced planar MOS capacitor reliability degradation is investigated in both via-last and via-middle through-silicon via (TSV) integration flows, with the capacitor electrically connected to the TSV. The leakage current and the breakdown voltage of the MOS capacitor are characterized to detect possible dielectric degradations caused by the electric charges generated during plasma-based processing steps: in the via last flow, during TSV dielectric liner dry etch and PVD metal barrier deposition steps; in the via-middle flow, during the backside TSV dry-etch reveal step. The effectiveness of a protection PN diode in preventing the MOS degradation is also evaluated.