A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates

In wide fan-in dynamic domino gates, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes which introduces a significant power penalty. In this paper, we propose a pulse domino technique to reduce the overall power consumption of a wide fan-in dynamic gate by having static-like switching behavior at the dynamic node, the gate input and the output terminals. Dynamic multiplexers designed and simulated in 90-nm CMOS are used to demonstrate the energy effectiveness of the proposed design style.