Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay

Summary form only given. A high performance 0.18 /spl mu/m CMOS technology with minimum 0.1 and nominal 0.13 /spl mu/m poly gate, physical 3 nm gate oxide, and 0.18 /spl mu/m local interconnect features operating at 1.5 V supply voltage is described with emphasis on the reduction of parasitic capacitances and resistances while maintaining high drive currents and low leakage currents to achieve a 15 ps unloaded ring oscillator delay. Coupling capacitance between gate and local interconnect is also discussed as a function of technology scaling as is 3 nm gate oxide reliability.