A novel area-efficient and full current-mode dual-port SRAM

This paper describes a novel area-efficient and full current-mode dual-port (DP) SRAM. It greatly reduced the area consumption of the DP-SRAM by using single-port (SP)-cell instead of 8T-DP-cell. Based on the full current-mode techniques for read/write operation, it also achieved low power consumption. A 1K times 8 proposed DP-SRAM is designed based on 0.18 mum CMOS technology. Its area is only 1.2 times of the SP-SRAM, and its power is 1.3 times of the SP-SRAM when the two ports simultaneously work at the same frequency of the SP-SRAM.