Comprehensive study on Chip to wafer hybrid bonding process for fine pitch high density heterogeneous applications

As the industry for 2.5D and 3D technology moving towards higher interconnect density and faster performance with tighter bump pitch at $\mathrm{20}\mu\mathrm{m}$ and below, there is a need to search and study a different bonding options and technology. The most promising technology is the Cu to Cu hybrid bonding technology. However, there are several process challenges in the bonding of the passivation and Cu interfaces either at room temperature or elevated temperature. The understanding on the hybrid bonding of the 2 different silicon surfaces is extremely important in order to achieve good and strong bonding interface with no voids. In this work, a $\mathrm{10}\times \mathrm{10}\text{mm}$ chip with Cu pad is used for the Chip to wafer hybrid bonding process. The Cu pad bump diameter is $\mathrm{6}\mu\mathrm{m}$ and the pad pitch is $\mathrm{12}\mu\mathrm{m}$ . Many assembly process such as the wafer dicing process, chemical-mechanical polishing (CMP) process for SiO wafers and Cu dishing, plasma cleaning process, bonding process and post bonding annealing process are critical for the chip to wafer hybrid bonding process. Process evaluation is done at each process steps. This paper presents the development in C2W hybrid bonding and demonstrates the low temperature annealing capability at $\mathrm{12} \mu\mathrm{m}$ Cu pad fine pitch applications.