Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Transconductance efficiency ( ${g}_{m}/{I}_{D}$ ) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of ${g}_{m}/{I}_{D}$ versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultrathin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the ${g}_{m}/{I}_{D}$ -based design methodologies usage in DG FDSOI transistors sizing.