A variable drivability (VD) output buffer for the system in a package (SIP) and high frequency wafer test

A system in a package (SIP) is another candidate of future embedded system chips against the system on a chip (SOC). The SIP has intra connections, which have a small I/O load. On the other hand, the high frequency wafer test has a large I/O load caused by the probe, Hi-Fix and coaxial cable. This paper makes these incompatible load problems clear and proposes a new output buffer to overcome them. A new variable drivability (VD) output buffer can provide the optimum driving ability for both the SIP intra-connection and the high frequency (over 100 MHz) wafer test. This proposed output buffer realizes a new SIP test flow containing a high frequency wafer test and a reduction of the total test cost of embedded DRAM chips by 35% compared with the SOC test cost.