A negative voltage generator for the sample-and-hold circuit in charge-domain pipelined ADCs

A negative voltage generator for the sample-and-hold (SH) circuit in charge-domain pipelined analog to digital converters (ADCs) based on brigade-bucket devices (BBDs) is presented in this paper. In the charge transfer phase of the BBD sample-and-hold circuit, a negative voltage is produced on the bottom plate of the sampling capacitor, which may result in serious problems that the resetting switches are shut off incompletely and the drain/substrate PN junctions are forward biased. In order to solve these problems, the resetting switches are realized with NMOS transistors in deep N-well. Additionally, a negative voltage generator is proposed to generate the control signals with suitable negative voltages for the gate and substrate nodes of the resetting switches in the charge transferring phase. The negative voltage generator is designed in SMIC 0.18-µm CMOS process. Simulated results show that the required negative voltage can be generated, which ensure the correct functions of the SH circuit. The simulated signal-to-noise ratio (SNR) of the whole SH circuit is 142 dB under a sampling frequency of 125 MHz.