A 32-GS/s Front-end Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the 4×8 two-stage interl...