Contraintes de réalisation d'un démonstrateur mixte FPGA-ADSP 21160 sur une application de Télécommunication : récepteur DVB-RCS

This article deals with the implementation phase of an embedded system. Specific problems connected to mixed architectures have been evaluated in a telecommunication application case. We have studied a QPSK demodulator (DVB-RCS) implemented on a platform combining a floating-point DSP and a FPGA. We have pointed out constraints related to hardware partitioning, data streams, code optimization and system testing. Some of these architecture problems appear only on models close to the final system. The use of a general purpose multiprocessor rack, allows shorter development stage, but in our case it would have masked data stream and code optimization problems.