A new approach for estimation of R DS(on) of power arrays: Extensions and experimental results

This paper presents the extensions and experimental validations of a new approach recently developed by the authors for accurate estimation of on-resistance (R DS(on) ) of large lateral power MOSFET switch layouts present in on-chip DC-DC converters. This approach exploits the highly symmetric and repetitive patterns of power MOSFET layouts to generate the extracted resistance netlist efficiently resulting significant speed up in resistance extraction process. The extracted resistance values in the interconnects are computed from the metal geometry using models that relate resistance values to the geometric parameters of the layout. Comparison of results with an industry standard EM solver tool as well as experimental measurements for power MOSFET layouts of W/L ratio 10 5 amply demonstrate the computational efficiency and accuracy of the approach establishing its applicability for industrial on-chip power array implementations.