A new shallow trench and planar gate MOSFET structure based on VDMOS technology

This paper proposes a new shallow trench and planar gate MOSFET (TPMOS) structure based on VDMOS technology, in which the shallow trench is located at the center of the n− drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.