The influence of surface preparation on low temperature HfO2 ALD on InGaAs (001) and (110) surfaces

Current logic devices rely on 3D architectures, such as the tri-gate field effect transistor (finFET), which utilize the (001) and (110) crystal faces simultaneously thus requiring passivation methods for the (110) face in order to ensure a pristine 3D surface prior to further processing. Scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), and correlated electrical measurement on MOSCAPs were utilized to compare the effects of a previously developed in situ pre-atomic layer deposition (ALD) surface clean on the InGaAs (001) and (110) surfaces. Ex situ wet cleans are very effective on the (001) surface but not the (110) surface. Capacitance voltage indicated the (001) surface with no buffered oxide etch had a higher Cmax hypothesized to be a result of poor nucleation of HfO2 on the native oxide. An in situ pre-ALD surface clean employing both atomic H and trimethylaluminum (TMA) pre-pulsing, developed by Chobpattana et al. and Carter et al. for the (001) surface, was demonstrated t...