An 11-bit Ring Amplifier Pipeline ADC with Settling-Time Improvement Scheme

In this paper, an 11-bit ring amplifier (RAMP) pipeline ADC with settling-time improvement scheme is proposed. A RAMP-based ADC is adopted to achieve the reduced current consumption and hardware area. Novel technique utilizing the highpass filter is incorporated to improve the settling time of the amplifier. Each stage consists of a 1.5-bit multiplying digital-to-analog (MDAC) and flash ADC (FADC) since the unity-gain frequency of RAMP is affected by the load of MDAC. The conventional sample and hold amplifier (SHA) is used instead of RAMP in order to relieve the nonlinear distortion at the first stage. The pipelined ADC is designed in a 65nm CMOS process. For a single supply voltage of 1.2V, total current consumption is 15.5mA. At the sampling rate of 100MS/sec, SNDR and ENOB are 66.83dB and 10.81bits, respectively.