Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications

Power delivery to the tier farthest away from the package in 3D VLSI is challenging. This is because the current provided by the package on the bottom is (1) first used by other tiers before it reaches the top, and (2) delivered using extremely small-size intra and inter-tier vias. Our solution is a tier partitioning method that assigns power hungry cells to the tier closer to the package, which is farther away from the heat spreader. Our study shows that this approach alleviates the IR-drop, power delivery network (PDN) resource usage, and power consumption in the top tier. Moreover, moving the cells to the bottom tier, unlike popular belief, does not cause any serious thermal issues. This is especially true in mobile applications, where heat is dissipated by both the heat spreader and printed circuit board. In summary, our tier-partitioning leads to 24.66% IR-drop reduction, 28.57% PDN resource reduction, and 4% wirelength reduction, with < 1°C increase in temperature.