Characterization and integration of a CVD porous SiOCH (k<2.5) with enhanced mechanical properties for 65 nm CMOS interconnects and below

Device performance for 65 nm node CMOS technology and beyond will require the integration of porous ultra-low-k materials with dielectric constant below 2.5, in order to reduce coupling effects between interconnect lines. This paper discusses the process development, the characterization (chemical composition and structure, porosity, mechanical and electrical characteristics), and the integration of a porous chemical vapor deposition dielectric with a dielectric constant lower than 2.5. An optimized material, characterized by a hardness of about 1 GPa in association with a porosity of 41% and a mean pore radius of 1.9 nm, was successfully integrated using a dual damascene architecture scheme in copper interconnects.