Old Web
English
Sign In
Acemap
>
Paper
>
A free-space optical solution for the on-chip global interconnect bottleneck: Experimental validation
A free-space optical solution for the on-chip global interconnect bottleneck: Experimental validation
2007
Rohit Nair
Keywords:
Interconnect bottleneck
Chip
Electrical engineering
Electronic engineering
Engineering
experimental validation
free space
Correction
Cite
Save
Machine Reading By IdeaReader
0
References
0
Citations
NaN
KQI
[]