A 10-bit pipelined ADC with improved S/H circuit for CMOS image sensor

A 10-bit pipelined ADC with an improved S/H circuit for CMOS image sensor is presented in this paper. The improved S/H circuit is proposed to adjust the range of the input signal, eliminate dark current noise and calibrate offset voltage. The dark current noise and offset voltage can be calibrated with a DAC feedback loop and two feedback capacitances. During the sample phase, a special modulation voltage is generated to widen the range of input signal. The simulation results show that the maximum error voltage to be calibrated is up to 0.5V. The ADC achieves a SNDR of 58.4dB and ENOB of 9.4bits at 30MHz sample rate. The DNL and INL are 0.27LSB and 0.48LSB respectively.