Design for Test and Hardware Security Utilizing Retention Loss of Memristors

Scan chains, as the most common design-for-testability (DFT) technique, provide a powerful way for structural testing of integrated circuits (ICs). However, they can be easily exploited by unauthorized parties to acquire critical design information. Scan-based attacks are one kind of side-channel attack that reveals the comprehensive information of IC chips. Reports have shown many successful scan-based attacks against the mainstream cryptographic systems, such as Rivest–Shamir–Adleman (RSA), Advanced Encryption Standard (AES), and so on. On the other hand, current countermeasures are limited to either the incomplete protection of scan information or significant redesign complexity. In this article, we propose a new secure scan chain design technique using memristor devices. By utilizing the natural and highly unpredictable degradation in memristor cells, the proposed technique can provide truly random scan confusion with a simple mechanism. Detailed circuit implementation is also presented and demonstrates 0.6% hardware, 2.4% timing overhead compared to an AES-256 circuit with about 100- $\mu \text{W}$ power overhead.