Characterization of metrology to device overlay offset and novel methods to minimize it

An after etch overlay measurement on device is typically used as a reference overlay as this is what determines the final overlay. The delta between on target overlay from after develop (ADI) and this reference overlay on device after etch (AEI) is known as the metrology to device offset (MTD). As the fab overlay is controlled by a run-to-run control of ADI overlay, it is preferred to minimize the MTD. The MTD concept in overlay metrology has long been present in the industry and many ways to mitigate this problem have been adopted (such as designing overlay target at ADI that has a similarly low aberration response as the device, or dialing in a static offset between ADI and AEI overlay, etc.). As overlay margins continue to shrink, existing methods start to show gaps and are insufficient to suppress the MTD to an acceptable level on the few most critical overlay layers. In order to address this gap, we need to deploy a much wider solution space that provides an integrated design-lithography-etch solution. In order to characterize the MTD, (assuming that target design in ADI has already minimized aberration response delta between target and device), it is important to understand that there are two major components to MTD: (1) an inaccuracy in ADI overlay (metrology artifacts mostly due to the presence of target asymmetry) and (2) etch to litho offset due to any post ADI added effects such as etch induced expansion and/or stress release etc. However, the above two components are strongly coupled and traditional characterization methods have difficulty in separating their contribution to the measurement. In this technical paper we will discuss novel methods (data driven as well as model-based) to decouple these and multi-lot results will show that MTD can be further minimized compared to traditional static correction between ADI and AEI.