Power-Efficient Code Converters Using Sub-Threshold Adiabatic Logic Ultra-Low-Power Applications

Power dissipation becomes a decisive parameter in VLSI design in modern-day ultra-low-power applications. Sub-threshold has shown its potential as more efficient logic for ultra-low energy-consuming circuits. Circuits using sub-threshold logic have more timing delay comparable to conventional CMOS logic. Here, code converter circuits are realized using sub-threshold adiabatic logic (SAL) by deploying Cadence 45 nm technology. An extensive simulation study has been carried out, and our study validates the improved circuit performance using sub-threshold adiabatic logic. The present work will facilitate researchers for circuit realization for energy-efficient code converter circuit applications.