Design and Simulation of Low Power Dynamic Logic

to design various circuit in vlsi ,day to day improvements have been introduced to make better of it in tems of area ,speed and power ...as like firstly static cmos was introduced with lowest static power disscipation but to make better of it further dynamic logic is introduced to preserver power consumption but it also has some disadvantages ..hence varios techniques is being introduced to make better dynamic logic on the basis of domino logic which already introduced to overcome the problems of dynamic logic ..similarly in this proposed paper new technique is introduced working on tanner eda tools known as single transistor type dynamic logic (STTDL) which uses either pmos or nmos.