Design and implementation of GPS baseband correlator

Correlator design is the core part of the GPS baseband processor design. In this paper, the idea of the modular is used to design the local NCO, pseudo-code generator, mixer, integral-clear filter, phase detector and loop filter. Each module is completed by Verilog and validated on the FPGA. An alternative true value operation is ultilized on the mixer to replace the multiplier operation of the input signal in this paper, thereby reducing the computational complexity. By initializing G2 register of the PN generator, it can remove the design of the phase selector. FPGA verification results show that the improved GPS baseband correlator can reduce resource consumption, accelerate the processing speed, and correctly demodulate the navigation data from input GPS signals.