Mining Latency Guarantees for RT-level Designs

Modern integrated circuits are often multi-core designs connected via communication elements like buses, bridges, and routers. Each of these communication elements requires a certain amount of time, called latency, for transferring data. When a system interacts cyber-physically with the real world via sensors and actuators guaranteeing that the communication meets certain latency requirements and thus ensuring sufficient throughput is crucial. In this paper, we present a pragmatic approach to mine temporal properties that capture the symbolic conditions under which transferring data between two communication end-points within a given restriction for the latency can be guaranteed. In a first case-study, temporal properties of an RTlevel bus bridge design were mined considering different latency requirements.