The fault-tolerant NoC techniques with FPGA

In this paper, we mainly study the key technical issues of Network-on-Chip (NoC), focusing on the analysis of typical NoC mapping problems, and making further research on the fault-aware NoC task mapping. Firstly, we study some critical problems in the design of NoC task mapping, then summarized a fault model, and finally, verified the related issues of NoC on verification platform and Field Programmable Gate Array (FPGA).