The role of growth temperature on the electron mobility of InAs/In$_x$Ga$_{1-x}$As selective area grown nanowires

Semiconductor nanowire networks are essential elements for a variety of gate-tunable quantum applications. Their relevance, however, depends critically on the material quality. In this work we study selective area growth (SAG) of highly lattice-mismatched InAs/In$_x$Ga$_{1-x}$As nanowires on insulating GaAs(001) substrates and address two key challenges: crystalline quality and compositional uniformity. We introduce optimization steps and show how misfit dislocations are guided away from the InAs active region and how Ga-In intermixing is kinetically limited with growth temperature. The optimization process leads to a more than twofold increase in electron mobility and shows an advancement toward realizing high quality gatable quantum wire networks.